1. Field of the Invention
This invention relates to MOSFET memory devices and more particularly to floating gate FET memory devices and manufacturing processes therefor.
2. Description of Related Art
U.S. Pat. No. 5,556,799 of Hong for a "Process for Fabricating A Flash EEPROM" shows a method for fabricating a flash EEPROM having a plurality of "U" shaped floating gates over which a control gate/word line structure spans a number of floating gates. Hong teaches that as flash EEPROM devices are made with finer resolutions, floating gate surface areas shrink. This decreases the capacitance of the effective capacitor between the floating gate layer and the control gate layer. The unwanted decrease in effective capacitance results in a reduction in the coupling ratio, which is a parameter that describes the coupling to the floating gate of the voltage present at the control gate of the device. The poor coupling of voltage to a floating gate limits the programming and accessing speed of the flash EEPROM device. Bit lines and drain regions are formed before the gate conductors are formed and so the devices provided do not have source/drain regions self-aligned with the gate conductors.
U.S. Pat. No. 5,496,753 of Sakurai et al. for "Method of Fabricating a Semiconductor Nonvolatile Storage Device" shows a method of forming an EEPROM memory device having a MONOS memory structure in which the gate is formed before the source/drain implants.
U.S. Pat. No. 5,459,091 of Hwang for "Method for Fabricating a Non-Volatile Memory Device" shows a method of forming an EEPROM memory device that has an "L" shape in which an "L" shaped gate conductor stack comprising a control gate and a floating gate is formed by etching away a vertical sidewall formed on the edge of a sacrificial CVD oxide film.